//加一计数器
//上升沿触发
//reset下降沿复位0
module counter (
    clk,
    res,
    y
);
input clk;
input res;
output[7:0] y;

reg [7:0] y;
wire [7:0] sum;
assign sum=y+1;

always @(posedge clk or negedge res)//时钟上升沿触发，res下降沿复位 
begin
    if (res==0) begin
        y<=0;
    end else begin
        y<=sum;
    end
end
endmodule

`timescale 1ns/10ps
module counter_tb ();
reg c;
reg r;
wire[7:0] yy;
counter counter (
    .clk(c),
    .res(r),
    .y(yy)
); 
initial begin
            c<=0;
            r<=0;
    #50     r<=1;
    #3000   r<=0;
    #3010   r<=1;
    #10000  $stop;
end
always #10 c=~c;




endmodule